1. Field of the Invention
The present invention relates to a circuit for detecting a drop of a power supply voltage, and more specifically to such a detecting circuit which is mainly composed of insulated-gate field-effect-transistors (called "IGFETs" in the specification) and which is used for an electrically erasable programmable memory (called "EEPROM" in the specification).
2. Description of Related Art
Since EEPROMs are electrically erasable and electrically programmable, the EEPROMs can be set to various modes shown in the following table by applying a high level signal or a low level signal to external input terminals labelled for example CE, WE and OE under a condition in which the EEPROMs is assembled in an actual apparatus or system.
TABLE 1 ______________________________________ TERMINAL MODE ##STR1## ##STR2## ##STR3## ##STR4## ______________________________________ READ L H L DATA OUTPUT WRITE L L H DATA INPUT STANDBY H X X HIGH IMPEDANCE WRITE INHIBIT X X H -- X H X ______________________________________
where "H" indicates a high level, "L" indicates a low level, and "X" indicates a high level or a low level.
Therefore, if a power supply is shut down or a power supply voltage drops down below a tolerable level due to a trouble of a system incorporating the EEPROM therein, a memory cell in the EEPROM is erroneously written or erased. In the above table, for example, when the EEPROM is in the standby mode in which the CE and OE terminals are at a high level and, the WE terminal is at a low level, if the power supply voltage drops, a voltage applied to the CE terminal is brought from the high level to a low level and a voltage applied to the OE terminal is also brought from the high level to a low level. At this time, assuming that a capacitive load of the OE terminal is ten times a capacitive load of the CE terminal, a voltage drop of the CE terminal is faster than that of the OE terminal. As a result, the EEPROM is instantly put in the write mode, and therefore, data appearing on the input/output (I/O) terminal of the EEPROM (in this case, the data is indefinite since the I/O terminal is in the high impedance condition) is erroneously written to a memory cell of a certain address of the EEPROM.
Therefore, in order to avoid the above mentioned erroneous writing caused due to the power supply voltage drop, the EEPROM has generally incorporated therein a circuit for detecting the power supply voltage drop, and has been designed to inhibit the writing when a power supply voltage drop is detected by the power supply voltage drop detection circuit.
Specifically, the power supply voltage drop detection circuit is to detect whether or not a power supply voltage Vcc drops not greater than a predetermined detection level Vcc(INV). For example, the power supply voltage drop detection circuit outputs a high level signal when Vcc&gt;Vcc(INV), and a low level signal when Vcc.ltoreq.Vcc(INV). The detection level Vcc(INV) is previously determined to be smaller than a tolerable level of the power supply voltage, in order to ensure that the EEPROM is never put in the write inhibit status under an ordinary use condition. In addition, the detection level Vcc(INV) is desired to be as stable as possible independently of a temperature of environment of the EEPROM and variation of device parameters caused at the stage of manufacturing. If the detection level Vcc(INV) becomes higher than the tolerable level, the EEPROM can no longer be written under the ordinary use condition. On the other hand, if the detection level Vcc(INV) is too low, the power supply voltage drop detection circuit may not accurately detect a power supply voltage drop, so that an erroneous writing would often occur due to the power supply voltage drop.
One typical conventional power supply voltage drop detection circuit has included a voltage divider circuit composed of three N-channel IGFETs series-connected between a power supply voltage line and ground, each of the N-channel IGFETs being connected in the form of an active load. A connection node between the N-channel IGFET having a source connected to the ground and another N-channel IGFET having a source connected to a drain of the source grounded N-channel IGFET is connected to a first inverter, which is cascaded to a second inverter.
With this arrangement, assuming that the three N-channel IGFETs have the same threshold Vth, if Vcc&gt;3 Vth, the voltage on the connection node concerned is higher than Vth, and therefore, the second inverter outputs a high level signal. On the other hand, if Vcc.ltoreq.3 Vth, the voltage on the connection node drops, and therefore, the second inverter outputs a low level signal. Therefore, in the power supply voltage drop detection circuit mentioned above, it can be said that the detection level Vcc(INV).congruent.3 Vth. In addition, as mentioned hereinbefore, it is desired that even if the temperature changes, Vcc(INV) (namely, 3 Vth) is as stable as possible. However, in fact, the threshold Vth has an apparently perceivable temperature dependency, and therefore, the temperature dependency of the detection level Vcc(INV).congruent.3 Vth is three times that of a single N-channel IGFET. As a result, in some example, Vcc(INV) is 3.42 V at 25.degree. C. and 2.85 V at 100.degree. C. Namely, Vcc(INV) will change by 0.57 V with a temperature variation of 75.degree. C.
As mentioned above, the conventional power supply voltage drop detection circuit is such that the detection level Vcc(INV) is set three times the threshold Vth of each N-channel IGFET. Therefore, if the threshold Vth of each N-channel IGFET changes from the rated value of 25.degree. C. by .DELTA.Vth because of a temperature variation, the detection level Vcc(INV) greatly changes by 3.DELTA.Vth. In other words, if the temperature lowers, the detection level Vcc(INV) increases, and therefore approaches a tolerable level of the power supply voltage (for example, 4.5 V or 5.5 V). On the other hand, if the temperature elevates, the detection level Vcc(INV) decreases, and therefore, the power supply voltage drop detection circuit is brought into a condition of not accurately detecting a power supply voltage drop.
Therefore, the conventional power supply voltage drop detection circuit has to have been designed to determine the detection level Vcc(INV) taking the temperature dependency of Vth into consideration, in order to ensure that the detection level Vcc(INV) at a low temperature exceeds the tolerable level of the power supply voltage. This has made it difficult to design the power supply voltage drop detection circuit. On the other hand, since the detection level Vcc(INV) becomes too low at an elevated temperature, it is not possible to prevent a malfunction of the EEPROM caused due to the power supply voltage drop, over a wide range of temperature. As a result, the range of use temperature of the system has to have been limited.